store - vhdl compare new input with old input -

how do it?

i new , sure easy enough can't seem figure out how

here pseudo code

port(x,y: in std_logic_vector (2 downto 0) -- 3 bit input counted eg ("000", "001", "010"... "111", "000" ...)     q_out : out integer); -- example  signal temp_q_out: integer;  when x (or y) increments -- part can't     temp_q_out <= temp_ q_out + 1;   case temp_q_out     when 0 q_out <= 7     when 1 q_out <= 12     when 2 q_out <= 4     when others q_out <= 100 

how make temp_q_out count when x or y increments , @ no other time? want output q_out 7 until x or y changes 12 till x or y changes again 2. happens output becomes 100 straight away.

any @ appreciated

cheers guys :-)

i don't think there safe way want asynchronous logic. assuming want synthesize this, need clock input. then, can add process stores previous values of x , y, , checks whether new value equal old value or not. here's example:

process(clk)   variable prev_x, prev_y : std_logic_vector(2 downto 0) := (others => '0'); begin   if rising_edge(clk)     if (x /= prev_x) or (y /= prev_y)       temp_q_out <= temp_q_out + 1;     end if;     prev_x := x;     prev_y := y;   end if; end process;