Boolean Logic & gate delays -

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assuming 2 gate-delays sum or carry function, estimate time ripple-through carry addition adders following word lengths:-

i) 4-bit ii) 8-bit iii) 16-bit

in notes have written: "delay word width times each bit stage delay (2 gate delays)". therefore:

i) 2*4 = 8 ii) 2*8 = 16  iii) 2*16 = 32

looking @ ripple carry adder wikipedia page: http://en.wikipedia.org/wiki/ripple_carry_adder#ripple-carry_adder

the formula used here different, can explain discrepancy between notes , wikipedia article. of 2 correct?

thanking in advance.

joe

as can see figure in linked wikipedia article, assumption simplification: full adder

the critical path c_out contains three gates, i.e. delays. however, need 3 delays first stage, since following c_in changes, leads critical path of 2 gates second , following stages.


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